As is known, a memory cell is typically read by biasing the gate terminal of the cell (via a word line to which the gate terminal is connected) to a reading voltage V.sub.PCX of predetermined value and by forcing a biasing current I.sub.f into a bit line, to which the drain terminal of the cell to be read is connected. When the selected cell is kept in the linear region, the following equation applies: EQU I.sub.f =K*(W/L)*[(V.sub.PCX -V.sub.th)-V.sub.DS /2]*V.sub.DS(1)
in which K is a constant related to the manufacturing process, W/L is the width/length dimensional relationship of the cell, V.sub.th is the threshold voltage of the cell (i.e., the minimum voltage to be applied between the gate and source terminals of the cell to start to conduct current) and V.sub.DS is the drain-source voltage across the cell.
When the cell is appropriately biased, the voltage V.sub.DS is constant and the term V.sub.DS /2 is negligible with respect to the term (V.sub.PCX -V.sub.th). Consequently, the current I.sub.f flowing through the cell is linearly dependent on the threshold voltage V.sub.th and (1) becomes: EQU I.sub.f =K*(W/L)*(V.sub.PCX -V.sub.th)*V.sub.DS (2)
Various circuits for reading the threshold voltage V.sub.th have been proposed. However, these circuits are not precise or rapid enough because the threshold value and the electrical characteristics of the cells are strongly dependent on temperature and because the cell has a low transconductance and high parasitic capacitances.